VHDL topics
12 short topics in IoT Embedded and Edge Devices. Each one is a single focused exercise with a clear piece of evidence at the end.
12 topics, one exercise each.
Work through them in order, or jump to the one you need.
These are draft topic outlines (draft; instructor review pending). Full lessons follow after review; ask Ajay if you need a topic sooner.
- 01
Signal and data-type representation
Demonstrate signal and data-type representation in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 02
Combinational logic
Demonstrate combinational logic in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 03
Sequential logic and clocking
Demonstrate sequential logic and clocking in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 04
Finite-state machines
Demonstrate finite-state machines in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 05
Module and interface composition
Demonstrate module and interface composition in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 06
Reset and initialization strategy
Demonstrate reset and initialization strategy in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 07
Timing and synchronization
Demonstrate timing and synchronization in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 08
Testbench construction
Demonstrate testbench construction in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 09
Simulation and waveform analysis
Demonstrate simulation and waveform analysis in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 10
Synthesis interpretation
Demonstrate synthesis interpretation in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 11
Hardware resource constraints
Demonstrate hardware resource constraints in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course → - 12
Interface and timing verification
Demonstrate interface and timing verification in a focused VHDL example; verify normal behavior and one edge or failure case. Keep the exercise bounded and record the behavior supported by the chosen version.
Open micro-course →
Learn the same ideas beyond VHDL.
These courses share topics with this one, so you can compare how each language or tool handles the same concept.
More in Specialist languages and industry programming.
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